1. Field
This technology relates generally to semiconductor devices, and more specifically to nonvolatile memories with program and erase operations.
2. Description of Related Art
Both FIGS. 1A and 1B show a charge-trapping memory cell with a substrate 170, first current-carrying terminal 150, second current-carrying terminal 160, bottom oxide 140, charge-trapping structure 130, top oxide 120, and gate 110. FIGS. 1A and 1B show a charge-trapping memory cell undergoing the establishment of a high threshold state in different parts of the charge-trapping structure. Representative top oxides include silicon dioxide and silicon oxynitride having a thickness of about 50 to 100 Angstroms, or other similar high dielectric constant materials including, for example Al2O3. Representative bottom oxides include silicon dioxide and silicon oxynitride having a thickness of about 30 to 100 Angstroms, or other similar high dielectric constant materials. Representative charge-trapping structures include silicon nitride having a thickness of about 30 to 90 Angstroms, or other similar high dielectric constant materials, including metal oxides such as Al2O3, HfO2, and others. The charge-trapping structure may be a discontinuous set of pockets or particles of charge-trapping material, or a continuous layer as shown in the drawing.
In FIG. 1A, the right part of the charge-trapping structure 130 undergoes a program operation to establish a low threshold state. The voltage of the gate 110 is −5 V. The voltage of the drain 160 is 5 V. The voltage of the source 150 is 0 V. The voltage of the substrate 170 is 0V. Consequently, the right part of the charge-trapping structure 130 has trapped charge 133. In FIG. 1B, the left part of the charge-trapping structure 130 undergoes a program operation to establish a low threshold state. The voltage of the gate 110 is −5 V. The voltage of the drain 160 is 0 V. The voltage of the source 150 is 5 V. The voltage of the substrate 170 is 0 V. Consequently, the left part of the charge-trapping structure 130 has trapped charge 133.
In FIG. 2A, the nonvolatile memory cell undergoes an erase operation. The voltage of the gate 210 is −8 V. The voltage of the drain 260 is 10 V. The voltage of the source 250 is 10 V. The voltage of the substrate 270 is 10 V. Consequently, the electrons move from the gate 210 to the charge trapping structure 230 and from the charge trapping structure 230 towards the substrate 270. In FIG. 2B, the nonvolatile memory cell undergoes an erase operation with reversed voltage polarities. The voltage of the gate 210 is 10 V. The voltage of the drain 260 is −8 V. The voltage of the source 250 is −8 V. The voltage of the substrate 270 is −8 V. Consequently, the electrons move to the gate 210 from the charge trapping structure 230 and to the charge trapping structure 230 from the substrate 270. The erase operation may also be carried out with a floating voltage at the drain 260 and/or the source 250.
FIG. 3 shows an example process flow of erasing a nonvolatile memory cell. In 310, a command to erase the nonvolatile memory cell is received. In 320, in response to the erase command, a biasing arrangement for erasing the nonvolatile memory cell is applied to the terminals of the nonvolatile memory cell. In 330, an erase verify test is performed to confirm that a sufficient amount of erasing has been performed. If the erase verify test fails, then the biasing arrangement for erasing the nonvolatile memory cell is applied again. If the erase verify test passes, then the erase process is successful and done 340.
FIGS. 4A, 4B, and 4C show graphs of the relative distribution of the number of nonvolatile memory cells at various threshold voltages corresponding to the programmed state and erased state. FIG. 4A shows, prior to an erase operation, some nonvolatile memory cells having threshold voltages in the range of 3.5 V to 4 V corresponding to the programmed state 410, and some nonvolatile memory cells having threshold voltages in the range of 5 V to 6 V corresponding to the erased state 420. FIG. 4B shows an erase operation being performed on both the nonvolatile memory cells having threshold voltages corresponding to the programmed state 410 and on the nonvolatile memory cells having threshold voltages corresponding to the erased state 420. As a result, the distribution of the nonvolatile memory cells originally in the programmed state 410 shifts to the erased state 415. Similarly, the distribution of the nonvolatile memory cells originally in the erased state 420 shifts to the erased state 425. FIG. 4C shows the actual distribution of threshold voltages of the nonvolatile memory cells in the erased state after the erase operation, which is the sum of distribution 415 and distribution 425, or distribution 430 in the range of 5 V to 7 V. Because the erase operation shifted not only the threshold voltages of the nonvolatile memory cells in the programmed state 410, but also the threshold voltages of the nonvolatile memory cells in the erased state 420, the result of the program-and-erase cycle is an undesirable wide distribution 430 of threshold voltages of nonvolatile memory cells in the erased state.
Therefore, it would be desirable to perform an erase operation on a nonvolatile memory cell while reducing the tendency of the distribution of threshold voltages of nonvolatile memory cells in the erased state to drift.